View 24C01SC-W08_2418111.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2004 microchip technology inc. ds21170e-page 1 24c01sc/24c02sc features: ? iso standard 7816 pad locations low-power cmos technology - 1 ma active current typical -10 a standby current typical at 5.5v organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8) 2-wire serial interface bus, i 2 c? compatible 100 khz and 400 khz compatibility self-timed write cycle (including auto-erase) page-write buffer for up to 8 bytes 2 ms typical write cycle time for page-write esd protection > 4 kv 1,000,000 e/w cycles ensured data retention > 200 years available for extended temperature ranges description: the microchip technology inc. 24c01sc and 24c02sc are 1k-bit and 2k-bit electrically erasable proms with bondpad positions optimized for smart card applications. the devices are organized as a single block of 128 x 8-bit or 256 x 8-bit memory with a two-wire serial interface. the 24c01sc and 24c02sc also have page-write capability for up to 8 bytes of data. die layout block diagram - commercial (c): 0c to +70c sda dc v cc scl v ss hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic sda scl v cc v ss 1k/2k 5.0v i 2 c ? serial eeproms for smart cards i 2 c is a trademark of philips corporation. not recommended for new designs ? please use 24lc01sc or 24lc02sc.
24c01sc/24c02sc ds21170e-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ........................................................................................................ -0.6v to v cc + 1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pads ............................................................................................................................... ....................... 4 kv table 1-1: dc characteristics figure 1-1: bus timing start/stop ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics v cc = +4.5v to +5.5v commercial (c): t a = 0c to +70c parameter symbol min. max. units conditions scl and sda pads: high level input voltage v ih .7 v cc ?? low level input voltage v il ?.3 v cc v hysteresis of schmidt trigger inputs v hys .05 v cc ?v (note 1) low level output voltage v ol ?.40vi ol = 3.0 ma, v cc = 4.5v input leakage current (scl) i li -10 10 av in = .1v to 5.5v output leakage current (sda) i lo -10 10 av out = .1v to 5.5v pin capacitance (all inputs/outputs) c in , c out ?10pfv cc = 5.0v (note 1) t a = 25c, f clk = 1 mhz operating current i cc write ? 3 ma v cc = 5.5v i cc read ? 1 ma vcc = 5.5v, scl = 400 khz standby current i ccs ?100 av cc = 5.5v, sda = scl = v cc note 1: this parameter is periodically sampled and not 100% tested. scl sda t su : sta t hd : sta s tart s top v hys t su : sto
? 2004 microchip technology inc. ds21170e-page 3 24c01sc/24c02sc table 1-2: ac characteristics figure 1-2: bus timing data parameter symbol min. max. units remarks clock frequency f clk ? 400 khz clock high time t high 600 ? ns clock low time t low 1300 ? ns sda and scl rise time t r ? 300 ns (note 1) sda and scl fall time t f ? 300 ns (note 1) start condition hold time t hd : sta 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0?ns (note 2) data input setup time t su : dat 100 ? ns stop condition setup time t su : sto 600 ? ns output valid from clock t aa ? 900 ns (note 2) bus free time t buf 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of 20 + 0.1 cb 250 ns (note 1) , cb = 100 pf input filter spike suppression (sda and scl pins) t sp ?50ns (note 3) write cycle time t wr ? 10 ms byte or page mode endurance ? 1m ? cycles 25c, vcc = 5v, block mode (note 4) note 1: not 100% tested. cb = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance ? model which can be obtained from microchip?s web site at www.microchip.com. scl sda in sda out t hd : sta t su : sta t f t high t r t su : sto t su : dat t hd : dat t buf t aa t hd : sta t aa t sp t low
24c01sc/24c02sc ds21170e-page 4 ? 2004 microchip technology inc. 2.0 functional description the 24c01sc/02sc supports a bidirectional two-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24c01sc/02sc works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first in first out fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 3-1: data transfer sequence on the serial bus note: the 24c01sc/02sc does not generate any acknowledge bits if an internal programming cycle is in progress. scl sda (a) (b) (d) (d) (c) (a) start condition address or acknowledge valid data allowed to change stop condition
? 2004 microchip technology inc. ds21170e-page 5 24c01sc/24c02sc 3.6 slave address after generating a start condition, the bus master trans- mits the slave address consisting of a 4-bit device code ( 1010 ) for the 24c01sc/02sc, followed by three ?don't care? bits. the eighth bit of slave address determines if the master device wants to read or write to the 24c01sc/02sc (figure 3-2). the 24c01sc/02sc monitors the bus for its corre- sponding slave address all the time. it generates an acknowledge bit if the slave address was true, and it is not in a programming mode. figure 3-2: control byte allocation 4.0 write operation 4.1 byte write following the start signal from the master, the device code (4 bits), the ?don't care? bits (3 bits), and the r/w bit, which is a logic low, is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmit- ted by the master is the word address and will be written into the address pointer of the 24c01sc/02sc. after receiving another acknowledge signal from the 24c01sc/02sc, the master device will transmit the data word to be written into the addressed memory location. the 24c01sc/02sc acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24c01sc/02sc will not generate acknowledge signals (figure 4-1). 4.2 page write the write control byte, word address, and the first data byte are transmitted to the 24c01sc/02sc in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to eight data bytes to the 24c01sc/02sc, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condi- tion. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order five bits of the word address remains constant. if the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (figure 4-2). operation control code chip select r/w read 1010 xxx 1 write 1010 xxx 0 x = don?t care r/w a 1010xxx read/write start slave address note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
24c01sc/24c02sc ds21170e-page 6 ? 2004 microchip technology inc. figure 4-1: byte write figure 4-2: page write s p s t a r t s t o p bus activity master sda line bus activity a c k a c k a c k control byte word address data s p bus activity master sda line bus activity s t a r t s t o p control byte word address (n) data n data n + 7 data n + 1 a c k a c k a c k a c k a c k
? 2004 microchip technology inc. ds21170e-page 7 24c01sc/24c02sc 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack, and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow 6.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. 6.1 current address read the 24c01sc/02sc contains an address counter that maintains the address of the last word accessed, inter- nally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24c01sc/ 02sc issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24c01sc/ 02sc discontinues transmission (figure 6-1). 6.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24c01sc/02sc as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then, the master issues the control byte again but with the r/w bit set to a one. the 24c01sc/ 02sc will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24c01sc/02sc discontinues transmission (figure 6-2). 6.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24c01sc/02sc transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24c01sc/02sc to transmit the next sequentially addressed 8-bit word (figure 6-3). to provide sequential reads the 24c01sc/02sc contains an internal address pointer which is incre- mented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes
24c01sc/24c02sc ds21170e-page 8 ? 2004 microchip technology inc. 6.4 noise protection the 24c01sc/02sc employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. figure 6-1: current address read figure 6-2: random read figure 6-3: sequential read sp bus activity master sda line bus activity s t a r t control byte data n a c k n o a c k s t o p s p s bus activity master sda line bus activity s t a r t s t o p control byte word address (n) data n a c k a c k n o a c k control byte a c k s t a r t p sda line bus activity s t o p control byte data n a c k n o a c k a c k a c k a c k data n + 1 data n + 2 data n + x bus activity master
? 2004 microchip technology inc. ds21170e-page 9 24c01sc/24c02sc 7.0 pad descriptions table 7-1: pad function table 7.1 sda serial address/data input/ output this is a bidirectional pad used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10k? for 100 khz, 2 k? for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 7.2 scl serial clock this input is used to synchronize the data transfer from and to the device. 7.3 dc don?t connect this pad is used for test purposes and should not be bonded out. it is pulled down to v ss through an internal resistor. 8.0 die characteristics figure 8-1 shows the die layout of the 24c01sc/02sc, including bondpad positions. table 8-1 shows the actual coordinates of the bondpad midpoints with respect to the center of the die. figure 8-1: die layout table 8-1: bondpad coordinates name function v ss ground sda serial address/data i/o scl serial clock v cc +4.5v to 5.5v power supply dc don?t connect pad name pad midpoint, x dir. pad midpoint, y dir. v ss -495.000 749.130 sda -605.875 -271.875 scl 479.875 -746.625 v cc 605.875 -261.375 note 1: dimensions are in microns. 2: center of die is at the 0,0 point. pdip sda dc v cc scl v ss
24c01sc/24c02sc ds21170e-page 10 ? 2004 microchip technology inc. appendix a: revision history revision e added note to page 1 header (not recommended for new designs). added on-line support page. updated document format.
? 2004 microchip technology inc. ds21170e-page 11 24c01sc/24c02sc on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
24c01sc/24c02sc ds21170e-page 12 ? 2004 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21170e 24c01sc/24c02sc 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. ds21170e-page 13 24c01sc/24c02sc product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx xxx pattern package temperature range device device 24c01sc: 1k i 2 c iso smart card die 24c02sc: 2k i 2 c iso smart card die temperature range blank = 0 c to +70 c package s = die in wafer pak w=wafer wf = sawed wafer on frame die thickness blank = 11 mils 08 = 8 mils other die thicknesses available, please consult factory. data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
24c01sc/24c02sc ds21170e-page 14 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21170e-page 15 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds21170e-page 16 ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 san jose 1300 terra bella avenue mountain view, ca 94043 tel: 650-215-1444 fax: 650-961-0286 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 706b wan tai bei hai bldg. no. 6 chaoyangmen bei str. beijing, 100027, china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building, no. 2 fengxiangnan road, ronggui town, shunde district, foshan city, guangdong 528303, china tel: 86-757-28395507 fax: 86-757-28395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-22290061 fax: 91-80-22290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands waegenburghtplein 4 nl-5152 jr, drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 05/28/04 w orldwide s ales and s ervice

▲Up To Search▲

Price & Availability of 24C01SC-W08

	To Download 24C01SC-W08 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .